Exemplary embodiments of the present invention relate to a semiconductor chip and a fabricating method thereof, and more particularly, to a semiconductor chip capable of being used in electronic products that have the features of light weight, slim structure, and compact size, and a fabricating method including through silicon via (TSV) formation.
As ever higher performance electronic products are fabricated in small sizes and needs of portable mobile products have increased, there is an increasing demand for an ultra-miniaturized semiconductor memory with a high capacity. In general, in order to increase a storage capacity of a semiconductor memory, it is possible to use a method for increasing a storage capacity of a semiconductor memory by increasing the degree of integration of a semiconductor chip, and a method for mounting and assembling a plurality of semiconductor chips in one semiconductor package. In the former case, much effort, cost, and time are required. However, in the latter case, it is possible to increase a storage capacity of a semiconductor memory only by changing a packaging method. Furthermore, since the latter case has advantages in terms of required cost and research development effort and time as compared with the former case, semiconductor memory fabrication companies have made an effort to increase storage capacity of a semiconductor memory device through multi-chip packaging in which a plurality of semiconductor chips are mounted in one semiconductor package.
A method for mounting a plurality of semiconductor chips in one semiconductor package may be classified to a method for horizontally mounting the semiconductor chips and a method for vertically mounting the semiconductor chips. However, to keep up the miniaturization trend of electronic products, most semiconductor memory fabrication companies have employed a stack-type multi-chip package in which semiconductor chips are vertically stacked.
Typically, a package structure using through silicon via (TSV) is used in a stack package. A package employing the through silicon via (TSV) has a structure in which through silicon vias are formed in each chip in a wafer level and physical and electrical connections between chips are made with the through silicon vias. In order to cope with multifunctional and high performance mobile appliances, and the like, research into a package employing an electrode has been actively conducted.
FIG. 1 is a sectional view of a through silicon via according to the conventional art. Referring to FIG. 1, a through silicon via 12 of a silicon wafer 10 includes a front electrode 14, a back electrode 16, and an insulation layer 18 for substantially preventing a leakage current between silicon and the back electrode 16. Since the diameter of the through silicon via 12 is reduced as semiconductor parts become smaller, an opening 18a of the insulation layer 18 may need to be small. If the opening 18a of the insulation layer 18 is not small, a silicon leakage part 10a occurs, resulting in leakage current. In order to substantially prevent the leakage current, a lithography process using a short wavelength and surface flatness may be needed. However, such equipment is expensive, thus increasing the product cost.